Blocking processing restrictions based on page indices

ABSTRACT

Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application contains subject matter which is related to thesubject matter of the following applications, each of which is assignedto the same assignee as this application. Each of the below listedapplications is hereby incorporated herein by reference in its entirety:

[0002] “FILTERING PROCESSOR REQUESTS BASED ON IDENTIFIERS,” Slegel etal., (IBM Docket No. POU920030047US1), Ser. No. ______, filed herewith;

[0003] “BLOCKING PROCESSING RESTRICTIONS BASED ON ADDRESSES,” Slegel etal., (IBM Docket No. POU920030049US1), Ser. No. ______, filed herewith;and

[0004] “INVALIDATING STORAGE, CLEARING BUFFER ENTRIES, AND ANINSTRUCTION THEREFOR,” Slegel et al., (IBM Docket No. POU920030050US1),Ser. No. ______, filed herewith.

TECHNICAL FIELD

[0005] This invention relates, in general, to processing within acomputing environment, and in particular, to blocking processingrestrictions of the computing environment, such that processing cancontinue despite the restrictions.

BACKGROUND OF THE INVENTION

[0006] The processing of a request by one processor of a computingenvironment may affect one or more other processors of the environment.For example, in a Symmetric Multiprocessor System (SMP) based on thez/Architecture of International Business Machines Corporation, Armonk,N.Y., a broadcast purge operation, such as an Invalidate Page TableEntry (IPTE) instruction, requires entries of one or more buffers (e.g.,Translation Lookaside Buffers (TLBs)) to be removed from the buffers inall processors of the environment. Furthermore, the architecturerequires the buffers to be purged atomically, such that no processor canobserve a new TLB entry, while some other processor observes an oldentry. Many other computer architectures also provide a similarmechanism.

[0007] One common implementation for the broadcast purge operationincludes the following: 1) all processors are quiesced (i.e., mostnormal processing operations are suspended, including accessing theTLB); 2) TLBs on all processors are purged of the appropriate entries;3) the common resource is changed (e.g., a page table entry in storagefor IPTE); and 4) finally, the quiesce is released and the processorscontinue their normal activities. Obviously, this implementation couldhave a major performance impact, especially for large SMPconfigurations, since all processors must be quiesced for the durationof the operation. In particular, it is common that one processor isexecuting some long running instruction that is not interruptible, so itcannot reach the quiesce state for some time. Thus, all other processorsare required to wait for this last processor to reach the quiesce statebefore the steps described above can be completed.

[0008] Some strides have been made in the above processing to enhanceperformance. For example, in U.S. Pat. No. 6,119,219, entitled “SystemSerialization With Early Release Of Individual Processor,” Webb et al.,Sep. 12, 2000, and U.S. Pat. No. 6,079,013, entitled “MultiprocessorSerialization With Early Release of Processors,” Webb et al., Jun. 20,2000, each of which is hereby incorporated herein by reference in itsentirety, a technique is described in which processors are potentiallyquiesced for a shorter period of time. For example, when a processorreceives a request, it immediately quiesces and then purges theappropriate entries in its own TLB. After the purge is complete, thisprocessor is allowed to continue processing subject to variousrestrictions. One of these restrictions includes that if the processormisses in its TLB, it is not permitted to perform address translation,but instead must stall until the quiesce is released. Only after thequiesce is released are all restrictions removed from the processors andprocessing can continue.

[0009] Thus, although attempts have been made to reduce the amount oftime processors are stalled, enhancements are still needed. For example,a need exists for a capability that enables processing restrictions tobe blocked, such that processing can continue, despite the restrictions.

SUMMARY OF THE INVENTION

[0010] The shortcomings of the prior art are overcome and additionaladvantages are provided through the provision of a method offacilitating processing of a computing environment. The method includes,for instance, determining whether address translation is to continuedespite a restriction prohibiting address translation; and continuingwith processing, in response to the determining.

[0011] In a further aspect of the present invention, a method offacilitating processing of a computing environment is provided. Themethod includes, for instance, obtaining, by a processing unit of thecomputing environment, an indication to stall processing, in response toa processing restriction; determining whether the processing restrictionis to be blocked; and continuing processing, in response to thedetermining.

[0012] System and computer program products corresponding to theabove-summarized methods are also described and claimed herein.

[0013] Additional features and advantages are realized through thetechniques of the present invention. Other embodiments and aspects ofthe invention are described in detail herein and are considered a partof the claimed invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The subject matter which is regarded as the invention isparticularly pointed out and distinctly claimed in the claims at theconclusion of the specification. The foregoing and other objects,features, and advantages of the invention are apparent from thefollowing detailed description taken in conjunction with theaccompanying drawings in which:

[0015]FIG. 1 depicts one embodiment of a computing environmentincorporating and using one or more aspects of the present invention;

[0016]FIG. 2 depicts one embodiment of further details associated with acontroller of FIG. 1, in accordance with an aspect of the presentinvention;

[0017]FIG. 3 depicts one embodiment of the logic associated withdetermining whether an operation is to be performed regardless of arestriction placed thereon, in accordance with an aspect of the presentinvention;

[0018]FIG. 4 pictorially depicts one example of a master processorexecuting an Invalidate Page Table Entry (IPTE) instruction and issuinga broadcast request to a controller, which then forwards the request toslave processors, in accordance with an aspect of the present invention;

[0019]FIG. 5 pictorially depicts one example of a slave processorresponding to the request sent by the controller of FIG. 4, inaccordance with an aspect of the present invention;

[0020]FIG. 6 pictorially depicts one example of a processing restrictionbeing placed on a slave processor and processing associated therewith,in accordance with an aspect of the present invention;

[0021]FIG. 7 pictorially depicts one example of further processing beingperformed by the processors in relation to the Invalidate Page TableEntry instruction, in accordance with an aspect of the presentinvention;

[0022]FIG. 8 pictorially depicts the master processor sending a releasequiesce request to the controller, in accordance with an aspect of thepresent invention; and

[0023]FIG. 9 pictorially depicts normal execution of the processors,since the quiesce has been released, in accordance with an aspect of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0024] In accordance with an aspect of the present invention, acapability is provided that enables processing within a computingenvironment to continue, despite a processing restriction indicatingthat processing is prohibited. As one example, address translation isallowed to be performed, subsequent to a buffer miss, although it isindicated as prohibited. A comparison of page indices, for instance,indicates whether the prohibition can be blocked.

[0025] One embodiment of a computing environment 100 incorporating andusing one or more aspects of the present invention is described withreference to FIG. 1. Computing environment 100 is based, for instance,on the z/Architecture offered by International Business MachinesCorporation, Armonk, N.Y. The z/Architecture is described in an IBM®publication entitled, “z/Architecture Principles of Operation,” IBMPublication No. SA22-7832-00, December 2000, which is herebyincorporated herein by reference in its entirety. (IBM® is a registeredtrademark of International Business Machines Corporation, Armonk, N.Y.,U.S.A. Other names used herein may be registered trademarks, trademarksor product names of International Business Machines Corporation or othercompanies.) In one example, a computing environment based on thez/Architecture includes an eServer zSeries offered by InternationalBusiness Machines Corporation, Armonk, N.Y.

[0026] As one example, computing environment 100 includes a centralprocessor complex (CPC) 102 coupled to a controller 120. Centralprocessor complex 102 includes, for instance, one or more partitions 104(e.g., logical partitions LP1-LPn), one or more central processors 106(e.g., CP1-CPm), and a hypervisor 108 (e.g., a logical partitionmanager), each of which is described below.

[0027] Each logical partition 104 is capable of functioning as aseparate system. That is, each logical partition can be independentlyreset, initially loaded with an operating system, if desired, andoperate with different programs. An operating system or applicationprogram running in a logical partition appears to have access to a fulland complete computer system, but in reality, only a portion of it isavailable. A combination of hardware and Licensed Internal Code(commonly referred to as microcode) keeps a program in a logicalpartition from interfering with a program in a different logicalpartition. This allows several different logical partitions to operateon a single physical processor in a time sliced manner. In thisparticular example, each logical partition has a resident operatingsystem 110, which may differ for one or more logical partitions. In oneembodiment, operating system 110 is the z/OS operating system offered byInternational Business Machines Corporation, Armonk, N.Y.

[0028] Central processors 106 are physical processor resources that areallocated to the logical partitions. For instance, a logical partition104 includes one or more logical processors, each of which representsall or a share of a physical processor resource 106 allocated to thepartition. The logical processors of a particular partition 104 may beeither dedicated to the partition, so that the underlying processorresource is reserved for that partition; or shared with anotherpartition, so that the underlying processor resource is potentiallyavailable to another partition.

[0029] Logical partitions 104 are managed by hypervisor 108 implementedby microcode running on processors 106. Logical partitions 104 andhypervisor 108 each comprise one or more programs residing in respectiveportions of central storage associated with the central processors. Oneexample of hypervisor 108 is the Processor Resource/Systems Manager(PR/SM), offered by International Business Machines Corporation, Armonk,N.Y.

[0030] Controller 120, which is coupled to the central processorcomplex, includes centralized logic responsible for arbitrating betweendifferent processors issuing requests. For instance, when controller 120receives a request, it determines that the requester is the masterprocessor for that request and that the other processors are slaveprocessors; it broadcasts messages; and otherwise, handles requests. Oneexample of a controller is described in U.S. Pat. No. 6,199,219,entitled “System Serialization With Early Release Of IndividualProcessor,” Webb et al., Sep. 12, 2000, which is hereby incorporatedherein by reference in its entirety. Further details are also describedwith reference to FIG. 2.

[0031]FIG. 2 depicts one example of a controller 200 coupled to aplurality of central processors (CPUs) 201. In this example, only twocentral processors are depicted. However, it will be understood thatmore than two processors may be coupled to controller 200.

[0032] Controller 200 includes various controls including, for instance,system serialization controls 202. The system serialization controls areused to insure that operations that are to be serialized, such asInvalidate Page Table Entry (IPTE) instructions, are serialized, in thatonly one such instruction is in progress at one time in the computingenvironment. It also monitors the sequence of events for that operation.

[0033] Controller 200 is coupled to each central processor via variousinterfaces. For instance, an interface 204 is used by the LicensedInternal Code in a central processor to send “control” commands to thecontroller, which specify an action to be taken, and to send “sense”commands, which return information from the controller. Anotherinterface is a response bus 206, which is used to return informationfrom the controller for the “sense” commands. The response bus is alsoused to communicate command status for “control” commands, and may beset from a plurality of sources within the controller, including thesystem serialization controls. A central processor can use thisinterface to sense the state of the system serialization controls incontroller 200.

[0034] A further interface is interface 208, which is used by thecontroller to send commands to each CPU. This may also be controlledfrom a plurality of sources within the controller, including systemserialization controls 202. A yet further interface is interface 210,which provides signals to cache controls 212 of central processor 201.Cache controls 212 process commands, in response to the signals. In oneexample, cache controls 212 process commands that affect one or morebuffers, such as Translation Lookaside Buffers (TLBs) 213, as describedin further detail below.

[0035] In addition to cache controls 212, central processor 201 includesvarious other controls, including, for instance, interrupt controls 220and execution controls 222. In response to particular events, interruptcontrols 220 cause an internal interruption to be pending in the CPU,which in turn, causes execution controls 222 to suspend programinstruction processing, at the next interruptible point. In response tothe interruption, execution controls 222 invokes a Licensed InternalCode routine to set a broadcast operation allowed latch 224 to enablecache controls 212 to process pending commands.

[0036] Central processor 201 also includes a CPU quiesced latch 226 thatindicates whether or not the central processor is quiesced.

[0037] The above described computing environment is only one example.Many variations are possible without departing from the spirit of thepresent invention. For example, one or more partitions can be running indifferent architecture modes. Further, as one example, the environmentneed not be based on the z/Architecture, but instead, can be based onother architectures offered by Intel, Sun Microsystems, as well asothers. Moreover, an environment may include an emulator (e.g., softwareor other emulation mechanisms), in which a particular architecture or asubset thereof is emulated. In such an environment, one or moreemulation functions of the emulator can implement one or more aspects ofthe present invention, even though a computer executing the emulator mayhave a different architecture than the capabilities being emulated. Asone example, in emulation mode, the specific instruction or operationbeing emulated is decoded, and an appropriate emulation function isbuilt to implement the individual instruction or operation.

[0038] Individual processors execute instructions, as well as handleother processing. At times, the processing of a particular instructionplaces processing restrictions on the processing of one or more otherprocessors of the computing environment. There are situations, however,when those restrictions may be ignored, in accordance with an aspect ofthe present invention. Thus, a processor may filter a processingrestriction, and block (i.e., ignore) that restriction, in certaincircumstances. This is described in further detail below.

[0039] One example described herein relates to the execution of anInvalidate Page Table Entry (IPTE) instruction. An instance of anInvalidate Page Table Entry instruction is described in an IBM®publication entitled, “z/Architecture Principles of Operation,” IBMPublication No. SA22-7832-00, December 2000, which is herebyincorporated herein by reference in its entirety.

[0040] The Invalidate Page Table Entry instruction causes one or moreprocessors to purge entries in a buffer relating to the instruction. Forinstance, each processor has associated therewith one or more buffers,referred to as Translation Lookaside Buffers (TLBs), located in theprocessor. The Translation Lookaside Buffers are used by a DynamicAddress Translation (DAT) mechanism to enhance performance, whentranslating virtual addresses to real addresses. That is, some of theinformation used by the Dynamic Address Translation mechanism ismaintained in the buffers for faster access. For example, variousinformation specified in region tables, segment tables and/or pagetables are maintained in the buffers.

[0041] To purge an entry in a buffer, processors within the environmentare placed in a quiesce state, such that data is not corrupted. While inthis quiesce state, restrictions are placed on those processors,indicating, for instance, that address translation cannot be performed,if there is a miss in their TLB. However, in accordance with an aspectof the present invention, this restriction can be filtered and ignored,such that processing may continue. This is described in further detailwith reference to FIGS. 3-9. In particular, FIG. 3 depicts oneembodiment of the logic associated with an aspect of the presentinvention, and FIGS. 4-9 provide further details for one particularexample, in which an IPTE instruction is executed.

[0042] Initially, referring to FIG. 3, a processor executing within acomputing environment becomes subject to processing restrictions, STEP300. In one example, this occurs when the processor is placed in aquiesce state. In response to being placed in a quiesce state, theprocessor continues processing under certain restrictions. For example,the processor is to stall processing, if the processor misses in one ormore of its TLBs.

[0043] The processor continues processing until it is faced with therestriction, STEP 302. For example, it continues processing until itmisses in its TLB. Then, in accordance with an aspect of the presentinvention, a determination is made as to whether the processor cancontinue with the operation, despite the restriction, INQUIRY 304. Thatis, a decision is made as to whether the restriction can be blocked. Inone example, this determination is made based on page indices. Forinstance, a comparison is made between a page index that is to be usedfor translation (e.g., address translation) and a page index previouslysaved by the processor. If the indices are equal, then processing isstalled, STEP 306. However, if the indices are unequal, then theoperation can be performed, despite the restriction, STEP 308.

[0044] Further details relating to the processing of one or more aspectsof the present invention are described with reference to FIGS. 4-9.Although three processors are depicted, it is understood that anynumbers of processors can be used. Referring to FIG. 4, a processor 400executing an instruction 402 (e.g., an IPTE instruction) issues abroadcast request 404 (e.g., a quiesce request) as part of processingthe instruction. The request is forwarded, in this example, to acontroller 406. The processor issuing the request is referred to hereinas the master processor, and the other processors are referred to asslave processors. The processors are coupled to controller 406.

[0045] In response to controller 406 receiving a request of a broadcastnature from the master processor, the controller forwards the request(408) to the slave processors. The processors process the request in anappropriate manner, which depends on, for example, the current state ofthe processors.

[0046] For example, as depicted in FIG. 5, CP2 is executing a longrunning instruction (500), and thus, does not respond to the quiescerequest at this time and the quiesce request remains pending for CP2. Onthe other hand, CP0 responds to the controller that has reached aquiesce point (502), and it performs an operation associated with thequiesce request. This operation includes purging entries from one ormore of its TLBs (504). Additionally, in accordance with an aspect ofthe present invention, CP0 saves at least a portion of the page index ofthe request for later use (506). In one example, a page index is anoffset of a given page table entry from the origin of the page table,and 4-6 bits of the page index are saved. However, in other examples,other numbers of bits, including the entire page index, may be saved.

[0047] Since CP0 indicated to the controller that it has reached aquiesce point, in one embodiment, the controller sets a signal for theprocessor (see FIG. 6). This signal is, for instance, a blocktranslations (blk_xlat) signal (600) indicating that the slave processoris not permitted to continue in the event of a TLB miss. That is, theslave processor is signaled that it is not permitted to perform DATtranslations in the event of a TLB miss. However, in accordance with anaspect of the present invention, further processing is performed todetermine if the signal can be ignored.

[0048] For example, when CP0 misses in its TLB (e.g., there is no entryin the TLB corresponding to the virtual address to be translated), itattempts to perform Dynamic Address Translation. During Dynamic AddressTranslation, it compares at least a portion of the page index of thepage it is to access with the saved page index it has from the broadcastIPTE operation. If they do not match, then the processor is allowed tocontinue translation and resume normal execution. For example, theprocessor can continue using parts of the virtual address and/or otherinformation to index into tables to obtain information usable in formingthe real address. Further, as part of normal execution, the processorcompletes this instruction, as well as processes other instructions.

[0049] However, if they do match, then the processor stalls and waitsfor the blk_xlat signal to drop. (In one example, comparisons areperformed at one or more steps during the translation, and processingcontinues or stalls, in response to the comparisons.)

[0050] With reference to FIG. 7, it is shown that CP0 is continuing toexecute instructions under the restrictions described above. Theserestrictions continue until the blk_xlat signal (700) drops. Further, itis shown that CP2 has finally finished its long running instruction andis able to take the quiesce interrupt. Thus, CP2 responds back to thecontroller that it is at a quiesce point (702). Further, it purges itsTLB of appropriate entries associated with the broadcast IPTE operationand saves at least a portion of the page index for later use (704).

[0051] In response to the controller receiving the quiesce indicationfrom CP2, the controller sets the blk_xlat signal for CP2 (706), and CP2is now under the same restrictions that CP0 has been under.Additionally, the controller responds to the quiesce master processor,CP1, that the last processor in the system has reached the quiescepoint, and the system is placed in a quiesce state (708).

[0052] Since the system is in a quiesce state, the master processorinvalidates the appropriate page table entries in storage (800—FIG. 8).In one example, this includes turning on an invalid bit in one or morepage table entries in storage. In response to the master processorcompleting the invalidation of the appropriate page table entries, itsends a signal to the controller indicating to release the quiesce(802). Meanwhile, CP0 and CP2 continue normal execution subject to thelimitations (804).

[0053] In response to the controller receiving the release indication,the controller releases the quiesce, and CP0, CP1 and CP2 resume normalexecution (900—FIG. 9) with no limitations. The blk_xlat signals thatwere previously active from the controller are no longer active.

[0054] Described in detail above is a capability that enablesrestrictions to be blocked (i.e., ignored) under certain conditions.This advantageously reduces the amount of quiesce stall time ofprocessors and enhances system performance. This performance enhancementcan be seen in many environments, including large SMP environments. Forinstance, one or more capabilities of the present invention improve onsystem performance, as follows. Previously for a 16-way SMP system, 10%of all time could be spent on quiescing the system and being stalledwaiting for blk_xlat to drop. This performance degradation wouldincrease at a rate roughly proportional to the square of the number ofprocessors in an SMP system. This is significantly reduced by using oneor more aspects of the present invention.

[0055] Although the above example is described with reference to an IPTEinstruction, one or more aspects of the present invention are applicableto other instructions, including those that are similar or equivalent tothe above instruction in the same architecture or differentarchitectures. In one example, one or more aspects of the presentinvention are applicable to an IDTE instruction, which is described in aU.S. application entitled “Invalidating Storage, Clearing BufferEntries, and An Instruction Therefor,” Slegel et al., filed herewith,which is hereby incorporated herein by reference in its entirety.

[0056] Many variations to the above embodiment are possible withoutdeparting from the spirit of the present invention. For example, one ormore aspects of the present invention are equally applicable to, forinstance, virtual machine emulation, in which one or more pageableentities (e.g., guests) execute on one or more processors. As oneexample, pageable guests are defined by the Start Interpretive Execution(SIE) architecture, one example of which is described in an IBM®publication entitled, “IBM System/370 Extended Architecture,” IBMPublication No. SA22-7095 (1985), which is hereby incorporated herein byreference in its entirety. In this example, both the host and guest areoperating in a virtual addressing environment, and the translationtables (e.g., page and segment tables) for the guest are stored atvirtual addresses in the host that are to be translated. That is, thepage table entries themselves are virtual addresses that are to betranslated to real addresses in the manner described herein. Thus,comparison of the page indices are performed, in one example, at eachlevel of translation.

[0057] Although the above example is described with reference to SIE andthe z/Architecture, one or more aspects of the present invention areequally applicable to other architectures and/or environments employingpageable entities or similar constructs.

[0058] In addition to the above variations, one or more aspects of thepresent invention are applicable to environments having mixedarchitecture modes. For example, in a logically partitioned environment,one physical processor can be executing code in one architecture mode,while another physical processor is executing code in anotherarchitecture mode. Additionally, one or more partitions can be executingpageable entities. A mixed architecture mode may alter the aboveprocessing, as indicated in the following table: Architecture Mode OfArchitecture Mode Action On Slave Master Processor Of Slave ProcessorProcessor ESA/390 ESA/390 No blocking ESA/390 z/Architecture Blockingpossible z/Architecture ESA/390 No blocking z/Architecturez/Architecture Blocking possible

[0059] In the above table, when the action on the slave processorindicates no blocking, then the restriction is not ignored and theblk_xlat signal is honored. However, in those situations where itindicates that blocking is possible, then the restriction may beblocked, as determined in accordance with an aspect of the presentinvention.

[0060] The various modes of architecture described above are onlyexamples. Other architecture modes and/or mixed architecture modes maybe supported without departing from the spirit of the present invention.

[0061] Moreover, the various embodiments described above are justexamples. There may be many variations to these embodiments withoutdeparting from the spirit of the present invention. For instance,although a logically partitioned environment is described herein, thisis only one example. Aspects of the invention are beneficial to manytypes of environments, including other environments that have aplurality of zones, and non-partitioned environments. Further, there maybe no central processor complexes, but yet, multiple processors coupledtogether. Yet further, one or more aspects of the invention areapplicable to single processor environments.

[0062] Although a particular environment is described herein, again,many variations to this environment can be implemented without departingfrom the spirit of the present invention. For example, if theenvironment is logically partitioned, then more or less logicalpartitions may be included in the environment. Further, there may bemultiple central processing complexes coupled together. These are onlysome of the variations that can be made without departing from thespirit of the present invention. Additionally, other variations arepossible. For example, although the controller described hereinserializes the instruction so that one broadcast instruction executes atone time, in another embodiment, multiple instructions may execute atone time. Further, the environment may include multiple controllers. Yetfurther, multiple quiesce requests (from one or more controllers) may beconcurrently outstanding in the system. In that scenario, multiple pageindices are saved and multiple comparisons are performed. Additionalvariations are also possible.

[0063] Advantageously, one or more aspects of the present invention canbe used to increase performance, along with one or more aspects of oneor more other inventions, which are described in a U.S. PatentApplication, entitled “Filtering Processor Requests Based OnIdentifiers,” Slegel et al., (IBM Docket No. POU920030047US1) filedherewith; and a U.S. Patent Application, entitled “Blocking ProcessingRestrictions Based On Addresses,” Slegel et al. (IBM Docket No.POU920030049US1) filed herewith, each of which is hereby incorporatedherein by reference in its entirety.

[0064] As used herein, the term “processing unit” includes pageableentities, such as guests; processors; emulators; and/or other similarcomponents. Moreover, the term “by a processing unit” includes on behalfof a processing unit. The term “obtaining” includes, but is not limitedto, receiving, having, being provided, receiving an indication of, etc.Yet further, the term “buffer” includes an area of storage, as well asdifferent types of data structures, including, but not limited to,arrays. Further, although the term “table” is used herein, this term isto cover various other data structures. The terms, buffer and table, arenot meant to be limiting to specific types of data structures.

[0065] The capabilities of the present invention can be implemented insoftware, firmware, hardware, or some combination thereof.

[0066] One or more aspects of the present invention can be included inan article of manufacture (e.g., one or more computer program products)having, for instance, computer usable media. The media has embodiedtherein, for instance, computer readable program code means or logic(e.g., instructions, code, commands, etc.) to provide and facilitate thecapabilities of the present invention. The article of manufacture can beincluded as a part of a computer system or sold separately.

[0067] Additionally, at least one program storage device readable by amachine embodying at least one program of instructions executable by themachine to perform the capabilities of the present invention can beprovided.

[0068] The flow diagrams depicted herein are just examples. There may bemany variations to these diagrams or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order, or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

[0069] Although preferred embodiments have been depicted and describedin detail herein, it will be apparent to those skilled in the relevantart that various modifications, additions, substitutions and the likecan be made without departing from the spirit of the invention and theseare therefore considered to be within the scope of the invention asdefined in the following claims.

What is claimed is:
 1. A method of facilitating processing of acomputing environment, said method comprising: determining whetheraddress translation is to continue despite a restriction prohibitingaddress translation; and continuing with processing, in response to thedetermining.
 2. The method of claim 1, wherein the determining comprisescomparing at least a portion of one page index with at least a portionof another page index, wherein a mismatch indicates continuing withprocessing.
 3. The method of claim 2, wherein the one page indexcomprises a page index to be used in address translation.
 4. The methodof claim 2, wherein the address translation is performed by a processingunit, and wherein the another page index comprises a page index relatingto a request obtained by the processing unit.
 5. The method of claim 4,wherein the processing unit comprises a processor.
 6. The method ofclaim 4, wherein the processing unit comprises a pageable entity.
 7. Themethod of claim 4, wherein the request comprises a broadcast purgeoperation initiated in response to processing by another processingunit.
 8. The method of claim 2, wherein the determining comprisescomparing at least a portion of the one page index with at least aportion of a plurality of another page indices, wherein a plurality ofmismatches indicates continuing with processing.
 9. The method of claim1, wherein the restriction comprises an indication prohibiting addresstranslation in response to a buffer miss.
 10. The method of claim 9,wherein the buffer is a translation lookaside buffer.
 11. The method ofclaim 1, further comprising obtaining, by a processing unit that is toperform the address translation, an indication of the restriction, inresponse to a quiesce request.
 12. The method of claim 11, wherein thequiesce request is in response to execution, by another processing unitof the computing environment, an instruction to invalidate a page entry.13. The method of claim 12, wherein the processing unit and the anotherprocessing unit are based on different architecture modes.
 14. Themethod of claim 12, wherein the processing unit and the anotherprocessing unit are based on the same architecture mode.
 15. The methodof claim 1, wherein the determining is performed by a pageable entity ofthe computing environment, and further comprising performing thedetermining in response to a translation of an address associated withthe pageable entity itself.
 16. A method of facilitating processing of acomputing environment, said method comprising: obtaining, by aprocessing unit of the computing environment, an indication to stallprocessing, in response to a processing restriction; determining whetherthe processing restriction is to be blocked; and continuing processing,in response to the determining.
 17. The method of claim 16, wherein theprocessing restriction comprises a prohibition of address translation,in response to a buffer miss.
 18. The method of claim 17, wherein thedetermining comprises comparing at least a portion of one page indexwith at least a portion of another page index, wherein a mismatchindicates blocking of the restriction.
 19. The method of claim 18,wherein the one page index comprises a page index to be used in addresstranslation.
 20. The method of claim 19, wherein the another page indexcomprises a page index relating to a request, an indication of which isobtained by the processing unit.
 21. The method of claim 20, wherein theprocessing unit comprises a processor.
 22. The method of claim 20,wherein the processing unit comprises a pageable entity.
 23. A system offacilitating processing of a computing environment, said systemcomprising: means for determining whether address translation is tocontinue despite a restriction prohibiting address translation; andmeans for continuing with processing, in response to the determining.24. The system of claim 23, wherein the means for determining comprisesmeans for comparing at least a portion of one page index with at least aportion of another page index, wherein a mismatch indicates continuingwith processing.
 25. The system of claim 24, wherein the one page indexcomprises a page index to be used in address translation.
 26. The systemof claim 24, wherein the address translation is performed by aprocessing unit, and wherein the another page index comprises a pageindex relating to a request obtained by the processing unit.
 27. Thesystem of claim 26, wherein the processing unit comprises a processor.28. The system of claim 26, wherein the processing unit comprises apageable entity.
 29. The system of claim 26, wherein the requestcomprises a broadcast purge operation initiated in response toprocessing by another processing unit.
 30. The system of claim 24,wherein the means for determining comprises means for comparing at leasta portion of the one page index with at least a portion of a pluralityof another page indices, wherein a plurality of mismatches indicatescontinuing with processing.
 31. The system of claim 23, wherein therestriction comprises an indication prohibiting address translation inresponse to a buffer miss.
 32. The system of claim 23, furthercomprising means for obtaining, by a processing unit that is to performthe address translation, an indication of the restriction, in responseto a quiesce request.
 33. The system of claim 32, wherein the quiescerequest is in response to execution, by another processing unit of thecomputing environment, an instruction to invalidate a page entry. 34.The system of claim 33, wherein the processing unit and the anotherprocessing unit are based on different architecture modes.
 35. Thesystem of claim 33, wherein the processing unit and the anotherprocessing unit are based on the same architecture mode.
 36. The systemof claim 23, wherein a pageable entity of the computing environmentcomprises the means for determining, and wherein the determining isperformed, in response to a translation of an address associated withthe pageable entity itself.
 37. A system of facilitating processing of acomputing environment, said system comprising: means for obtaining, by aprocessing unit of the computing environment, an indication to stallprocessing, in response to a processing restriction; means fordetermining whether the processing restriction is to be blocked; andmeans for continuing processing, in response to the determining.
 38. Thesystem of claim 37, wherein the processing restriction comprises aprohibition of address translation, in response to a buffer miss. 39.The system of claim 38, wherein the means for determining comprisesmeans for comparing at least a portion of one page index with at least aportion of another page index, wherein a mismatch indicates blocking ofthe restriction.
 40. The system of claim 39, wherein the one page indexcomprises a page index to be used in address translation.
 41. The systemof claim 40, wherein the another page index comprises a page indexrelating to a request, an indication of which is obtained by theprocessing unit.
 42. A system of facilitating processing of a computingenvironment, said system comprising: a processing unit to determinewhether address translation is to continue despite a restrictionprohibiting address translation; and the processing unit to continuewith processing, in response to the determining.
 43. A system offacilitating processing of a computing environment, said systemcomprising: a processing unit of the computing environment to obtain anindication to stall processing, in response to a processing restriction;the processing unit to determine whether the processing restriction isto be blocked, and to continue processing, in response to thedetermining.
 44. At least one program storage device readable by amachine embodying at least one program of instructions executable by themachine to perform a method of facilitating processing of a computingenvironment, said method comprising: determining whether addresstranslation is to continue despite a restriction prohibiting addresstranslation; and continuing with processing, in response to thedetermining.
 45. The at least one program storage device of claim 44,wherein the determining comprises comparing at least a portion of onepage index with at least a portion of another page index, wherein amismatch indicates continuing with processing.
 46. The at least oneprogram storage device of claim 45, wherein the one page index comprisesa page index to be used in address translation.
 47. The at least oneprogram storage device of claim 45, wherein the address translation isperformed by a processing unit, and wherein the another page indexcomprises a page index relating to a request obtained by the processingunit.
 48. The at least one program storage device of claim 47, whereinthe processing unit comprises a processor.
 49. The at least one programstorage device of claim 47, wherein the processing unit comprises apageable entity.
 50. The at least one program storage device of claim47, wherein the request comprises a broadcast purge operation initiatedin response to processing by another processing unit.
 51. The at leastone program storage device of claim 45, wherein the determiningcomprises comparing at least a portion of the one page index with atleast a portion of a plurality of another page indices, wherein aplurality of mismatches indicates continuing with processing.
 52. The atleast one program storage device of claim 44, wherein the restrictioncomprises an indication prohibiting address translation in response to abuffer miss.
 53. The at least one program storage device of claim 44,wherein said method further comprises obtaining, by a processing unitthat is to perform the address translation, an indication of therestriction, in response to a quiesce request.
 54. The at least oneprogram storage device of claim 53, wherein the quiesce request is inresponse to execution, by another processing unit of the computingenvironment, an instruction to invalidate a page entry.
 55. The at leastone program storage device of claim 54, wherein the processing unit andthe another processing unit are based on different architecture modes.56. The at least one program storage device of claim 54, wherein theprocessing unit and the another processing unit are based on the samearchitecture mode.
 57. The at least one program storage device of claim44, wherein the determining is performed by a pageable entity of thecomputing environment, and wherein said method further comprisesperforming the determining in response to a translation of an addressassociated with the pageable entity itself.
 58. At least one programstorage device readable by a machine embodying at least one program ofinstructions executable by the machine to perform a method offacilitating processing of a computing environment, said methodcomprising: obtaining, by a processing unit of the computingenvironment, an indication to stall processing, in response to aprocessing restriction; determining whether the processing restrictionis to be blocked; and continuing processing, in response to thedetermining.
 59. The at least one program storage device of claim 58,wherein the processing restriction comprises a prohibition of addresstranslation, in response to a buffer miss.
 60. The at least one programstorage device of claim 59, wherein the determining comprises comparingat least a portion of one page index with at least a portion of anotherpage index, wherein a mismatch indicates blocking of the restriction.61. The at least one program storage device of claim 60, wherein the onepage index comprises a page index to be used in address translation. 62.The at least one program storage device of claim 61, wherein the anotherpage index comprises a page index relating to a request, an indicationof which is obtained by the processing unit.